DvCon India 2017

After its successful launch in 2014, the Design and Verification Conference & Exhibition India will be back in 2017! DVCon India 2017 provides an excellent platform to share knowledge, experience and best practices covering Electronic System Level Design & Verification for IP and SOC, VIP development and Virtual Prototyping for Embedded Software development and debug.

Sponsored by Accellera Systems Initiative, the conference provides multiple opportunities to interact with industry experts delivering keynote speeches, invited talks, tutorials, panel discussions, technical paper presentations, poster sessions and exhibits from ecosystem partners. The attendees will also get the latest information on various Accellera standards for system design, modelling and verification. These standards include UVM, SystemC (and its variants like SystemC-AMS, SCV, CCI, Synthesis subset), SystemVerilog, PSL, Assertions for AMS, Verilog, IP-XACT, OCP and many more.

The 2-day event will be attended by industry leaders, system architects, verification experts, SoC integrators, chip designers, IP developers, VIP developers and firmware engineers. The conference has two parallel tracks:

ESL Track: SystemC related topics such as Pre-Si SW development and debug using virtual prototypes of electronic systems and SoCs, architectural exploration, power and performance analysis for use cases, high level synthesis, model interoperable standards and more.

DV Track: Design & Verification languages, methodologies based on SystemVerilog, Verilog, UVM and technologies such as Formal Verification, Hardware Acceleration, Emulation and prototyping, along with the most widely used simulation and more.